----

--十进制计数器(count10.vhd)--

----

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_ARITH.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

----

ENTITY COUNT10 IS

PORT(CLK,CLR,ENA:IN STD_LOGIC;

QOUT:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)

);

END COUNT10;

----

ARCHITECTURE BEHAV PROCESS.html" target="_blank" title="PROCESS">PROCESS(CLK,CLR,ENA)

VARIABLE TMP:INTEGER RANGE 0 TO 10;

BEGIN

IF CLR='1' THEN

TMP:=0;

ELSIF CLK'EVENT AND CLK='1' THEN

IF ENA='1' THEN

TMP:=TMP+1;

IF TMP=10 THEN

TMP:=0;

END IF;

END IF;

END IF;

QOUT<=CONV_STD_LOGIC_VECTOR(TMP,4);

END process;

END BEHAV;

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----

--扫描信号发生器（count8.vhd）--

----

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_ARITH.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

----

ENTITY COUNT8 IS

port(CLK:IN STD_LOGIC;

QOUT:OUT STD_LOGIC_VECTOR(2 DOWNTO 0)

);

END COUNT8;

----

ARCHITECTURE BEHAV THEN

TMP<=TMP+1;

IF TMP=8 THEN

TMP<=0;

END IF;

END IF;

QOUT<=CONV_STD_LOGIC_VECTOR(TMP,3);

END PROCESS.html" target="_blank" title="PROCESS">PROCESS;

END BEHAV;

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----

--七段译码器（deLED.vhd）--

----

library ieee;

use ieee.std_logic_1164.all;

----

entity deled is

port(

datain:in std_logic_vector(3 downto 0);

qout:out std_logic_vector(6 downto 0)

);

end deled;

----

architecture func;

elsif datain= "0001" then qout<="0110000";

elsif datain= "0010" then qout<="1101101";

elsif datain= "0011" then qout<="1111001";

elsif datain= "0100" then qout<="0110011";

elsif datain= "0101" then qout<="1011011";

elsif datain= "0110" then qout<="1011111";

elsif datain= "0111" then qout<="1110000";

elsif datain= "1000" then qout<="1111111";

elsif datain= "1001" then qout<="1111011";

else null;

end if;

end process;

end func;

--＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝

--＝＝＝＝＝＝＝＝＝＝＝顶层文件描述＝＝＝＝＝＝＝＝＝＝＝＝＝

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----

--scan.vhd--

----

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

----

ENTITY SCAN IS

PORT(CLKK,CLK_SEL,CLRR,ENAA:IN STD_LOGIC;

SELOUT:OUT STD_LOGIC_VECTOR(2 DOWNTO 0);

QOUT:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)

);

END SCAN;

----

ARCHITECTURE BEHAV 发生器的调用；

PORT(CLK:IN STD_LOGIC;

QOUT:OUT STD_LOGIC_VECTOR(2 DOWNTO 0)

);

END COMPONENT;

----

--定义第三个元件--

COMPONENT DELED --定义第三个元件：七段通用译码器的调用；

port(

datain:in std_logic_vector(3 downto 0);

qout:out std_logic_vector(6 downto 0)

);

END COMPONENT;

----

--定义信号--

SIGNAL S1:STD_LOGIC_VECTOR(3 DOWNTO 0);

----

--元件例化体开始--

BEGIN

U1:COUNT10 PORT MAP(CLKK,CLRR,ENAA,S1); --例化第一个元件；

U2:DELED PORT MAP(S1,QOUT); --例化第二个元件；

U3:COUNT8 PORT MAP(CLK_SEL,SELOUT); --例化第三个元件；

END BEHAV;

----

--程序结束××--

----