uboot 下S3C6410 的LCD 显示-EDA365

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uboot 下S3C6410 的LCD 显示

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标签:
lcd
uboot
显示
s3c6410

cf_console.c中属于框架，基本不用改动，添加lcd，主要是通过video_hw_init()来实现lcd控制器的初始化。

具体工作：

1、smdk6410的修改

#if 1

//enable LCD display

#define CONFIG_CMD_BMP

#define CONFIG_VIDEO

#define CONFIG_VIDEO_S3C64X0

#define CONFIG_VIDEO_LOGO //display Linux Logo in upper left corner

#define VIDEO_FB_16BPP_WORD_SWAP //for BMP logo

#define CONFIG_VIDEO_SW_CURSOR //Draws a cursor after the last character.No blinking is provided.

//#define CONFIG_VIDEO_BMP_LOGO //use bmp_logo instead of linux_logo

//#define CONFIG_CONSOLE_EXTRA_INFO

//#define CONFIG_CONSOLE_CURSOR //on/off drawing cursor is done with delay loop in VIDEO_TSTC_FCT

//#define CONFIG_CONSOLE_TIME

#define CONFIG_CFB_CONSOLE

#define CONFIG_SYS_CONSOLE_IS_IN_ENV

//#define CFG_CONSOLE_INFO_QUIET

//#define VIDEO_FB_LITTLE_ENDIAN

#define CONFIG_SPLASH_SCREEN //enable splash screen support,implicitly enable U-Boot Bitmap Support.

#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (1024*768+1024+100) /* 100 = slack */

#define CONFIG_VIDEO_BMP_GZIP //Gzip compressed BMP image support

#define CONFIG_CMD_UNZIP

#define LCD_VIDEO_ADDR 0x57a00000

#define LCD_VIDEO_BACKGROUND

#if defined(LCD_VIDEO_BACKGROUND)

#define LCD_VIDEO_BACKGROUND_ADDR (0x57600000)

#define LCD_VIDEO_BACKGROUND_LOADADDR (0x57500000)

#define LCD_VIDEO_BACKGROUND_LOADSIZE (0x80000)

#define LCD_VIDEO_BACKGROUND_ALPHA (0xa)

#define LCD_VIDEO_BACKGROUND_IN_NAND

//#define LCD_VIDEO_BACKGROUND_IN_MMC

#define LCD_VIDEO_BACKGROUND_FLASH_ADDR (0x10000000)

#endif

#define CONFIG_SYS_VIDEO_VCLOCK_HZ (133000000)

//RAM_TEXT = 0x57e00000

/*for PC-keyboard*/

#define VIDEO_KBD_INIT_FCT 0

#define VIDEO_TSTC_FCT serial_tstc

#define VIDEO_GETC_FCT serial_getc

#endif /*enable LCD display*/

#define CONFIG_EXTRA_ENV_SETTINGS \ //串口信息输出到lcd上

"stdin=serial\0" \

"stdout=vga\0" \

"stderr=serial\0"

2、include/asm-arm/arch-s3c64xx下建立regs-fb.h

#define VIDCON0_INTERLACE (1 << 29)

#define VIDCON0_VIDOUT_MASK (0x3 << 26)

#define VIDCON0_VIDOUT_SHIFT (26)

#define VIDCON0_VIDOUT_RGB (0x0 << 26)

#define VIDCON0_VIDOUT_TV (0x1 << 26)

#define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)

#define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)

#define VIDCON0_L1_DATA_MASK (0x7 << 23)

#define VIDCON0_L1_DATA_SHIFT (23)

#define VIDCON0_L1_DATA_16BPP (0x0 << 23)

#define VIDCON0_L1_DATA_18BPP16 (0x1 << 23)

#define VIDCON0_L1_DATA_18BPP9 (0x2 << 23)

#define VIDCON0_L1_DATA_24BPP (0x3 << 23)

#define VIDCON0_L1_DATA_18BPP (0x4 << 23)

#define VIDCON0_L1_DATA_16BPP8 (0x5 << 23)

#define VIDCON0_L0_DATA_MASK (0x7 << 20)

#define VIDCON0_L0_DATA_SHIFT (20)

#define VIDCON0_L0_DATA_16BPP (0x0 << 20)

#define VIDCON0_L0_DATA_18BPP16 (0x1 << 20)

#define VIDCON0_L0_DATA_18BPP9 (0x2 << 20)

#define VIDCON0_L0_DATA_24BPP (0x3 << 20)

#define VIDCON0_L0_DATA_18BPP (0x4 << 20)

#define VIDCON0_L0_DATA_16BPP8 (0x5 << 20)

#define VIDCON0_PNRMODE_MASK (0x3 << 17)

#define VIDCON0_PNRMODE_SHIFT (17)

#define VIDCON0_PNRMODE_RGB (0x0 << 17)

#define VIDCON0_PNRMODE_BGR (0x1 << 17)

#define VIDCON0_PNRMODE_SERIAL_RGB (0x2 << 17)

#define VIDCON0_PNRMODE_SERIAL_BGR (0x3 << 17)

#define VIDCON0_CLKVALUP (1 << 16)

#define VIDCON0_CLKVAL_F_MASK (0xff << 6)

#define VIDCON0_CLKVAL_F_SHIFT (6)

#define VIDCON0_CLKVAL_F_LIMIT (0xff)

#define VIDCON0_CLKVAL_F(_x) ((_x) << 6)

#define VIDCON0_VLCKFREE (1 << 5)

#define VIDCON0_CLKDIR (1 << 4)

#define VIDCON0_CLKSEL_MASK (0x3 << 2)

#define VIDCON0_CLKSEL_SHIFT (2)

#define VIDCON0_CLKSEL_HCLK (0x0 << 2)

#define VIDCON0_CLKSEL_LCD (0x1 << 2)

#define VIDCON0_CLKSEL_27M (0x3 << 2)

#define VIDCON0_ENVID (1 << 1)

#define VIDCON0_ENVID_F (1 << 0)

//#define VIDCON1 (0x04)

#define VIDCON1_LINECNT_MASK (0x7ff << 16)

#define VIDCON1_LINECNT_SHIFT (16)

#define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff)

#define VIDCON1_VSTATUS_MASK (0x3 << 13)

#define VIDCON1_VSTATUS_SHIFT (13)

#define VIDCON1_VSTATUS_VSYNC (0x0 << 13)

#define VIDCON1_VSTATUS_BACKPORCH (0x1 << 13)

#define VIDCON1_VSTATUS_ACTIVE (0x2 << 13)

#define VIDCON1_VSTATUS_FRONTPORCH (0x0 << 13)

#define VIDCON1_INV_VCLK (1 << 7)

#define VIDCON1_INV_HSYNC (1 << 6)

#define VIDCON1_INV_VSYNC (1 << 5)

#define VIDCON1_INV_VDEN (1 << 4)

/* VIDCON2 */

//#define VIDCON2 (0x08)

#define VIDCON2_EN601 (1 << 23)

#define VIDCON2_TVFMTSEL_SW (1 << 14)

#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12)

#define VIDCON2_TVFMTSEL1_SHIFT (12)

#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)

#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)

#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)

#define VIDCON2_ORGYCbCr (1 << 8)

#define VIDCON2_YUVORDCrCb (1 << 7)

/* PRTCON (S3C6410, S5PC100)

* Might not be present in the S3C6410 documentation,

* but tests prove it's there almost for sure; shouldn't hurt in any case.

#define PRTCON (0x0c)

#define PRTCON_PROTECT (1 << 11)

/* VIDTCON0 */

#define VIDTCON0_VBPDE_MASK (0xff << 24)

#define VIDTCON0_VBPDE_SHIFT (24)

#define VIDTCON0_VBPDE_LIMIT (0xff)

#define VIDTCON0_VBPDE(_x) ((_x) << 24)

#define VIDTCON0_VBPD_MASK (0xff << 16)

#define VIDTCON0_VBPD_SHIFT (16)

#define VIDTCON0_VBPD_LIMIT (0xff)

#define VIDTCON0_VBPD(_x) ((_x) << 16)

#define VIDTCON0_VFPD_MASK (0xff << 8)

#define VIDTCON0_VFPD_SHIFT (8)

#define VIDTCON0_VFPD_LIMIT (0xff)

#define VIDTCON0_VFPD(_x) ((_x) << 8)

#define VIDTCON0_VSPW_MASK (0xff << 0)

#define VIDTCON0_VSPW_SHIFT (0)

#define VIDTCON0_VSPW_LIMIT (0xff)

#define VIDTCON0_VSPW(_x) ((_x) << 0)

/* VIDTCON1 */

#define VIDTCON1_VFPDE_MASK (0xff << 24)

#define VIDTCON1_VFPDE_SHIFT (24)

#define VIDTCON1_VFPDE_LIMIT (0xff)

#define VIDTCON1_VFPDE(_x) ((_x) << 24)

#define VIDTCON1_HBPD_MASK (0xff << 16)

#define VIDTCON1_HBPD_SHIFT (16)

#define VIDTCON1_HBPD_LIMIT (0xff)

#define VIDTCON1_HBPD(_x) ((_x) << 16)

#define VIDTCON1_HFPD_MASK (0xff << 8)

#define VIDTCON1_HFPD_SHIFT (8)

#define VIDTCON1_HFPD_LIMIT (0xff)

#define VIDTCON1_HFPD(_x) ((_x) << 8)

#define VIDTCON1_HSPW_MASK (0xff << 0)

#define VIDTCON1_HSPW_SHIFT (0)

#define VIDTCON1_HSPW_LIMIT (0xff)

#define VIDTCON1_HSPW(_x) ((_x) << 0)

//#define VIDTCON2 (0x18)

#define VIDTCON2_LINEVAL_MASK (0x7ff << 11)

#define VIDTCON2_LINEVAL_SHIFT (11)

#define VIDTCON2_LINEVAL_LIMIT (0x7ff)

#define VIDTCON2_LINEVAL(_x) ((_x) << 11)

#define VIDTCON2_HOZVAL_MASK (0x7ff << 0)

#define VIDTCON2_HOZVAL_SHIFT (0)

#define VIDTCON2_HOZVAL_LIMIT (0x7ff)

#define VIDTCON2_HOZVAL(_x) ((_x) << 0)

/* WINCONx */

#define WINCONx_ENLOCAL (1 << 22)

#define WINCONx_BITSWP (1 << 18)

#define WINCONx_BYTSWP (1 << 17)

#define WINCONx_HAWSWP (1 << 16)

#define WINCONx_WSWP (1 << 15)

#define WINCONx_InRGB_YCC (1 << 13)

#define WINCONx_BURSTLEN_MASK (0x3 << 9)

#define WINCONx_BURSTLEN_SHIFT (9)

#define WINCONx_BURSTLEN_16WORD (0x0 << 9)

#define WINCONx_BURSTLEN_8WORD (0x1 << 9)

#define WINCONx_BURSTLEN_4WORD (0x2 << 9)

#define WINCONx_ENWIN (1 << 0)

#define WINCON0_BPPMODE_MASK (0xf << 2)

#define WINCON0_BPPMODE_SHIFT (2)

#define WINCON0_BPPMODE_1BPP (0x0 << 2)

#define WINCON0_BPPMODE_2BPP (0x1 << 2)

#define WINCON0_BPPMODE_4BPP (0x2 << 2)

#define WINCON0_BPPMODE_8BPP_PALETTE (0x3 << 2)

#define WINCON0_BPPMODE_16BPP_565 (0x5 << 2)

#define WINCON0_BPPMODE_16BPP_1555 (0x7 << 2)

#define WINCON0_BPPMODE_18BPP_666 (0x8 << 2)

#define WINCON0_BPPMODE_24BPP_888 (0xb << 2)

#define WINCON1_BLD_PIX (1 << 6)

#define WINCON1_ALPHA_SEL (1 << 1)

#define WINCON1_BPPMODE_MASK (0xf << 2)

#define WINCON1_BPPMODE_SHIFT (2)

#define WINCON1_BPPMODE_1BPP (0x0 << 2)

#define WINCON1_BPPMODE_2BPP (0x1 << 2)

#define WINCON1_BPPMODE_4BPP (0x2 << 2)

#define WINCON1_BPPMODE_8BPP_PALETTE (0x3 << 2)

#define WINCON1_BPPMODE_8BPP_1232 (0x4 << 2)

#define WINCON1_BPPMODE_16BPP_565 (0x5 << 2)

#define WINCON1_BPPMODE_16BPP_A1555 (0x6 << 2)

#define WINCON1_BPPMODE_16BPP_I1555 (0x7 << 2)

#define WINCON1_BPPMODE_18BPP_666 (0x8 << 2)

#define WINCON1_BPPMODE_18BPP_A1665 (0x9 << 2)

#define WINCON1_BPPMODE_19BPP_A1666 (0xa << 2)

#define WINCON1_BPPMODE_24BPP_888 (0xb << 2)

#define WINCON1_BPPMODE_24BPP_A1887 (0xc << 2)

#define WINCON1_BPPMODE_25BPP_A1888 (0xd << 2)

#define WINCON1_BPPMODE_28BPP_A4888 (0xd << 2)

/* S5PV210 */

#define SHADOWCON (0x34)

#define SHADOWCON_WINx_PROTECT(_win) (1 << (10 + (_win)))

/* DMA channels (all windows) */

#define SHADOWCON_CHx_ENABLE(_win) (1 << (_win))

/* Local input channels (windows 0-2) */

#define SHADOWCON_CHx_LOCAL_ENABLE(_win) (1 << (5 + (_win)))

#define VIDOSDxA_TOPLEFT_X_MASK (0x7ff << 11)

#define VIDOSDxA_TOPLEFT_X_SHIFT (11)

#define VIDOSDxA_TOPLEFT_X_LIMIT (0x7ff)

#define VIDOSDxA_TOPLEFT_X(_x) ((_x) << 11)

#define VIDOSDxA_TOPLEFT_Y_MASK (0x7ff << 0)

#define VIDOSDxA_TOPLEFT_Y_SHIFT (0)

#define VIDOSDxA_TOPLEFT_Y_LIMIT (0x7ff)

#define VIDOSDxA_TOPLEFT_Y(_x) ((_x) << 0)

#define VIDOSDxB_BOTRIGHT_X_MASK (0x7ff << 11)

#define VIDOSDxB_BOTRIGHT_X_SHIFT (11)

#define VIDOSDxB_BOTRIGHT_X_LIMIT (0x7ff)

#define VIDOSDxB_BOTRIGHT_X(_x) ((_x) << 11)

#define VIDOSDxB_BOTRIGHT_Y_MASK (0x7ff << 0)

#define VIDOSDxB_BOTRIGHT_Y_SHIFT (0)

#define VIDOSDxB_BOTRIGHT_Y_LIMIT (0x7ff)

#define VIDOSDxB_BOTRIGHT_Y(_x) ((_x) << 0)

/* For VIDOSD[1..4]C */

#define VIDISD14C_ALPHA0_R(_x) ((_x) << 20)

#define VIDISD14C_ALPHA0_G_MASK (0xf << 16)

#define VIDISD14C_ALPHA0_G_SHIFT (16)

#define VIDISD14C_ALPHA0_G_LIMIT (0xf)

#define VIDISD14C_ALPHA0_G(_x) ((_x) << 16)

#define VIDISD14C_ALPHA0_B_MASK (0xf << 12)

#define VIDISD14C_ALPHA0_B_SHIFT (12)

#define VIDISD14C_ALPHA0_B_LIMIT (0xf)

#define VIDISD14C_ALPHA0_B(_x) ((_x) << 12)

#define VIDISD14C_ALPHA1_R_MASK (0xf << 8)

#define VIDISD14C_ALPHA1_R_SHIFT (8)

#define VIDISD14C_ALPHA1_R_LIMIT (0xf)

#define VIDISD14C_ALPHA1_R(_x) ((_x) << 8)

#define VIDISD14C_ALPHA1_G_MASK (0xf << 4)

#define VIDISD14C_ALPHA1_G_SHIFT (4)

#define VIDISD14C_ALPHA1_G_LIMIT (0xf)

#define VIDISD14C_ALPHA1_G(_x) ((_x) << 4)

#define VIDISD14C_ALPHA1_B_MASK (0xf << 0)

#define VIDISD14C_ALPHA1_B_SHIFT (0)

#define VIDISD14C_ALPHA1_B_LIMIT (0xf)

#define VIDISD14C_ALPHA1_B(_x) ((_x) << 0)

/* Video buffer addresses */

#define VIDW_BUF_START(_buff) (0xA0 + ((_buff) * 8))

#define VIDW_BUF_START1(_buff) (0xA4 + ((_buff) * 8))

#define VIDW_BUF_END(_buff) (0xD0 + ((_buff) * 8))

#define VIDW_BUF_END1(_buff) (0xD4 + ((_buff) * 8))

#define VIDW_BUF_SIZE(_buff) (0x100 + ((_buff) * 4))

#define VIDW_BUF_SIZE_OFFSET_MASK (0x1fff << 13)

#define VIDW_BUF_SIZE_OFFSET_SHIFT (13)

#define VIDW_BUF_SIZE_OFFSET_LIMIT (0x1fff)

#define VIDW_BUF_SIZE_OFFSET(_x) ((_x) << 13)

#define VIDW_BUF_SIZE_PAGEWIDTH_MASK (0x1fff << 0)

#define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT (0)

#define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT (0x1fff)

#define VIDW_BUF_SIZE_PAGEWIDTH(_x) ((_x) << 0)

/* Interrupt controls and status */

#define VIDINTCON0_FIFOINTERVAL_MASK (0x3f << 20)

#define VIDINTCON0_FIFOINTERVAL_SHIFT (20)

#define VIDINTCON0_FIFOINTERVAL_LIMIT (0x3f)

#define VIDINTCON0_FIFOINTERVAL(_x) ((_x) << 20)

#define VIDINTCON0_INT_SYSMAINCON (1 << 19)

#define VIDINTCON0_INT_SYSSUBCON (1 << 18)

#define VIDINTCON0_INT_I80IFDONE (1 << 17)

#define VIDINTCON0_FRAMESEL0_MASK (0x3 << 15)

#define VIDINTCON0_FRAMESEL0_SHIFT (15)

#define VIDINTCON0_FRAMESEL0_BACKPORCH (0x0 << 15)

#define VIDINTCON0_FRAMESEL0_VSYNC (0x1 << 15)

#define VIDINTCON0_FRAMESEL0_ACTIVE (0x2 << 15)

#define VIDINTCON0_FRAMESEL0_FRONTPORCH (0x3 << 15)

#define VIDINTCON0_FRAMESEL1 (1 << 13)

#define VIDINTCON0_FRAMESEL1_MASK (0x3 << 13)

#define VIDINTCON0_FRAMESEL1_NONE (0x0 << 13)

#define VIDINTCON0_FRAMESEL1_BACKPORCH (0x1 << 13)

#define VIDINTCON0_FRAMESEL1_VSYNC (0x2 << 13)

#define VIDINTCON0_FRAMESEL1_FRONTPORCH (0x3 << 13)

#define VIDINTCON0_INT_FRAME (1 << 12)

#define VIDINTCON0_FIFIOSEL_MASK (0x7f << 5)

#define VIDINTCON0_FIFIOSEL_SHIFT (5)

#define VIDINTCON0_FIFIOSEL_WINDOW0 (0x1 << 5)

#define VIDINTCON0_FIFIOSEL_WINDOW1 (0x2 << 5)

#define VIDINTCON0_FIFOLEVEL_MASK (0x7 << 2)

#define VIDINTCON0_FIFOLEVEL_SHIFT (2)

#define VIDINTCON0_FIFOLEVEL_TO25PC (0x0 << 2)

#define VIDINTCON0_FIFOLEVEL_TO50PC (0x1 << 2)

#define VIDINTCON0_FIFOLEVEL_TO75PC (0x2 << 2)

#define VIDINTCON0_FIFOLEVEL_EMPTY (0x3 << 2)

#define VIDINTCON0_FIFOLEVEL_FULL (0x4 << 2)

#define VIDINTCON0_INT_FIFO_MASK (0x3 << 0)

#define VIDINTCON0_INT_FIFO_SHIFT (0)

#define VIDINTCON0_INT_ENABLE (1 << 0)

//#define VIDINTCON1 (0x134)

#define VIDINTCON1_INT_I180 (1 << 2)

#define VIDINTCON1_INT_FRAME (1 << 1)

#define VIDINTCON1_INT_FIFO (1 << 0)

/* Window colour-key control registers */

#define WKEYCON (0x140) /* 6410,V210 */

#define WKEYCON0 (0x00)

#define WKEYCON1 (0x04)

#define WxKEYCON0_KEYBL_EN (1 << 26)

#define WxKEYCON0_KEYEN_F (1 << 25)

#define WxKEYCON0_DIRCON (1 << 24)

#define WxKEYCON0_COMPKEY_MASK (0xffffff << 0)

#define WxKEYCON0_COMPKEY_SHIFT (0)

#define WxKEYCON0_COMPKEY_LIMIT (0xffffff)

#define WxKEYCON0_COMPKEY(_x) ((_x) << 0)

#define WxKEYCON1_COLVAL_MASK (0xffffff << 0)

#define WxKEYCON1_COLVAL_SHIFT (0)

#define WxKEYCON1_COLVAL_LIMIT (0xffffff)

#define WxKEYCON1_COLVAL(_x) ((_x) << 0)

/* Window blanking (MAP) */

#define WINxMAP_MAP (1 << 24)

#define WINxMAP_MAP_COLOUR_MASK (0xffffff << 0)

#define WINxMAP_MAP_COLOUR_SHIFT (0)

#define WINxMAP_MAP_COLOUR_LIMIT (0xffffff)

#define WINxMAP_MAP_COLOUR(_x) ((_x) << 0)

#define WPALCON_PAL_UPDATE (1 << 9)

#define WPALCON_W1PAL_MASK (0x7 << 3)

#define WPALCON_W1PAL_SHIFT (3)

#define WPALCON_W1PAL_25BPP_A888 (0x0 << 3)

#define WPALCON_W1PAL_24BPP (0x1 << 3)

#define WPALCON_W1PAL_19BPP_A666 (0x2 << 3)

#define WPALCON_W1PAL_18BPP_A665 (0x3 << 3)

#define WPALCON_W1PAL_18BPP (0x4 << 3)

#define WPALCON_W1PAL_16BPP_A555 (0x5 << 3)

#define WPALCON_W1PAL_16BPP_565 (0x6 << 3)

#define WPALCON_W0PAL_MASK (0x7 << 0)

#define WPALCON_W0PAL_SHIFT (0)

#define WPALCON_W0PAL_25BPP_A888 (0x0 << 0)

#define WPALCON_W0PAL_24BPP (0x1 << 0)

#define WPALCON_W0PAL_19BPP_A666 (0x2 << 0)

#define WPALCON_W0PAL_18BPP_A665 (0x3 << 0)

#define WPALCON_W0PAL_18BPP (0x4 << 0)

#define WPALCON_W0PAL_16BPP_A555 (0x5 << 0)

#define WPALCON_W0PAL_16BPP_565 (0x6 << 0)

3、include/asm-arm/arch-s3c64xx下建立regs-fb-v4.h

#include

#define S3C_FB_MAX_WIN (5) /* number of hardware windows available. */

#define VIDCON1_FSTATUS_EVEN (1 << 15)

/* Video timing controls */

//#define VIDTCON0 (0x10)

//#define VIDTCON1 (0x14)

//#define VIDTCON2 (0x18)

/* Window position controls */

#define WINCON(_win) (0x20 + ((_win) * 4))

/* OSD1 and OSD4 do not have register D */

#define VIDOSD_BASE (0x40)

//#define VIDINTCON0 (0x130)

/* WINCONx */

#define WINCONx_CSCWIDTH_MASK (0x3 << 26)

#define WINCONx_CSCWIDTH_SHIFT (26)

#define WINCONx_CSCWIDTH_WIDE (0x0 << 26)

#define WINCONx_CSCWIDTH_NARROW (0x3 << 26)

#define WINCONx_ENLOCAL (1 << 22)

#define WINCONx_BUFSTATUS (1 << 21)

#define WINCONx_BUFSEL (1 << 20)

#define WINCONx_BUFAUTOEN (1 << 19)

#define WINCONx_YCbCr (1 << 13)

#define WINCON1_LOCALSEL_CAMIF (1 << 23)

#define WINCON2_LOCALSEL_CAMIF (1 << 23)

#define WINCON2_BLD_PIX (1 << 6)

#define WINCON2_ALPHA_SEL (1 << 1)

#define WINCON2_BPPMODE_MASK (0xf << 2)

#define WINCON2_BPPMODE_SHIFT (2)

#define WINCON2_BPPMODE_1BPP (0x0 << 2)

#define WINCON2_BPPMODE_2BPP (0x1 << 2)

#define WINCON2_BPPMODE_4BPP (0x2 << 2)

#define WINCON2_BPPMODE_8BPP_1232 (0x4 << 2)

#define WINCON2_BPPMODE_16BPP_565 (0x5 << 2)

#define WINCON2_BPPMODE_16BPP_A1555 (0x6 << 2)

#define WINCON2_BPPMODE_16BPP_I1555 (0x7 << 2)

#define WINCON2_BPPMODE_18BPP_666 (0x8 << 2)

#define WINCON2_BPPMODE_18BPP_A1665 (0x9 << 2)

#define WINCON2_BPPMODE_19BPP_A1666 (0xa << 2)

#define WINCON2_BPPMODE_24BPP_888 (0xb << 2)

#define WINCON2_BPPMODE_24BPP_A1887 (0xc << 2)

#define WINCON2_BPPMODE_25BPP_A1888 (0xd << 2)

#define WINCON2_BPPMODE_28BPP_A4888 (0xd << 2)

#define WINCON3_BLD_PIX (1 << 6)

#define WINCON3_ALPHA_SEL (1 << 1)

#define WINCON3_BPPMODE_MASK (0xf << 2)

#define WINCON3_BPPMODE_SHIFT (2)

#define WINCON3_BPPMODE_1BPP (0x0 << 2)

#define WINCON3_BPPMODE_2BPP (0x1 << 2)

#define WINCON3_BPPMODE_4BPP (0x2 << 2)

#define WINCON3_BPPMODE_16BPP_565 (0x5 << 2)

#define WINCON3_BPPMODE_16BPP_A1555 (0x6 << 2)

#define WINCON3_BPPMODE_16BPP_I1555 (0x7 << 2)

#define WINCON3_BPPMODE_18BPP_666 (0x8 << 2)

#define WINCON3_BPPMODE_18BPP_A1665 (0x9 << 2)

#define WINCON3_BPPMODE_19BPP_A1666 (0xa << 2)

#define WINCON3_BPPMODE_24BPP_888 (0xb << 2)

#define WINCON3_BPPMODE_24BPP_A1887 (0xc << 2)

#define WINCON3_BPPMODE_25BPP_A1888 (0xd << 2)

#define WINCON3_BPPMODE_28BPP_A4888 (0xd << 2)

#define VIDINTCON0_FIFIOSEL_WINDOW2 (0x10 << 5)

#define VIDINTCON0_FIFIOSEL_WINDOW3 (0x20 << 5)

#define VIDINTCON0_FIFIOSEL_WINDOW4 (0x40 << 5)

//#define DITHMODE (0x170)

#define WINxMAP(_win) (0x180 + ((_win) * 4))

#define DITHMODE_R_POS_MASK (0x3 << 5)

#define DITHMODE_R_POS_SHIFT (5)

#define DITHMODE_R_POS_8BIT (0x0 << 5)

#define DITHMODE_R_POS_6BIT (0x1 << 5)

#define DITHMODE_R_POS_5BIT (0x2 << 5)

#define DITHMODE_G_POS_MASK (0x3 << 3)

#define DITHMODE_G_POS_SHIFT (3)

#define DITHMODE_G_POS_8BIT (0x0 << 3)

#define DITHMODE_G_POS_6BIT (0x1 << 3)

#define DITHMODE_G_POS_5BIT (0x2 << 3)

#define DITHMODE_B_POS_MASK (0x3 << 1)

#define DITHMODE_B_POS_SHIFT (1)

#define DITHMODE_B_POS_8BIT (0x0 << 1)

#define DITHMODE_B_POS_6BIT (0x1 << 1)

#define DITHMODE_B_POS_5BIT (0x2 << 1)

#define DITHMODE_DITH_EN (1 << 0)

//#define WPALCON (0x1A0)

/* Palette control */

/* Note for S5PC100: you can still use those macros on WPALCON (aka WPALCON_L),

* but make sure that WPALCON_H W2PAL-W4PAL entries are zeroed out */

#define WPALCON_W4PAL_16BPP_A555 (1 << 8)

#define WPALCON_W3PAL_16BPP_A555 (1 << 7)

#define WPALCON_W2PAL_16BPP_A555 (1 << 6)

4、修改driver/video/videomodes.c，添加相应分辨率

const struct ctfb_vesa_modes vesa_modes[VESA_MODES_COUNT]添加如下成员

{0x31B, RES_MODE_1280x1024, 24},

{0x211, RES_MODE_240x320, 16},

{0x212, RES_MODE_480x272, 16},

{0x213, RES_MODE_800x480, 16},

const struct ctfb_res_modes res_mode_init[RES_MODES_COUNT]添加成员函数

{240, 320, 90000, 1, 4, 1, 1, 30, 4, 0, FB_VMODE_NONINTERLACED},

{480, 272, 75000, 2, 3, 1, 1, 40, 1, 0, FB_VMODE_NONINTERLACED},

{800, 480, 50000, 2, 2, 2, 2, 41, 4, 0, FB_VMODE_NONINTERLACED},

5、修改driver/video/videomodes.h

修改#define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x212//0x301

添加：

#define RES_MODE_240x320 6

#define RES_MODE_480x272 7

#define RES_MODE_800x480 8

#define RES_MODES_COUNT 9

修改：#define VESA_MODES_COUNT 22//19

6、include/asm-arm/s3c6400.h

添加

#define ELFIN_FB_BASE 0x77100000

#define LCD_SEL 0

#define LCD_SEL_MASK 0x03

static inline s3c64xx_fb *s3c64xx_get_base_fb(void)

{

return (s3c64xx_fb *)(ELFIN_FB_BASE);

}

7、include/asm-arm/s3c64x0.h

添加：

typedef struct {

volatile u32 VIDCON0;

volatile u32 VIDCON1;

volatile u32 VIDCON2;

volatile u8 res1[4];

volatile u32 VIDTCON0;

volatile u32 VIDTCON1;

volatile u32 VIDTCON2;

volatile u8 res2[4];

volatile u32 WINCON0;

volatile u32 WINCON1;

volatile u32 WINCON2;

volatile u32 WINCON3;

volatile u32 WINCON4;

volatile u8 res3[12];

volatile u32 VIDOSD0A;

volatile u32 VIDOSD0B;

volatile u32 VIDOSD0C;

volatile u8 res4[4];

volatile u32 VIDOSD1A;

volatile u32 VIDOSD1B;

volatile u32 VIDOSD1C;

volatile u32 VIDOSD1D;

volatile u32 VIDOSD2A;

volatile u32 VIDOSD2B;

volatile u32 VIDOSD2C;

volatile u32 VIDOSD2D;

volatile u32 VIDOSD3A;

volatile u32 VIDOSD3B;

volatile u32 VIDOSD3C;

volatile u8 res5[4];

volatile u32 VIDOSD4A;

volatile u32 VIDOSD4B;

volatile u32 VIDOSD4C;

volatile u8 res6[20];

volatile u32 VIDW00ADD0B0;

volatile u32 VIDW00ADD0B1;

volatile u32 VIDW01ADD0B0;

volatile u32 VIDW01ADD0B1;

volatile u32 VIDW02ADD0;

volatile u8 res7[4];

volatile u32 VIDW03ADD0;

volatile u8 res8[4];

volatile u32 VIDW04ADD0;

volatile u8 res9[12];

volatile u32 VIDW00ADD1B0;

volatile u32 VIDW00ADD1B1;

volatile u32 VIDW01ADD1B0;

volatile u32 VIDW01ADD1B1;

volatile u32 VIDW02ADD1;

volatile u8 res10[4];

volatile u32 VIDW03ADD1;

volatile u8 res11[4];

volatile u32 VIDW04ADD1;

volatile u8 res12[12];

volatile u32 VIDW00ADD2;

volatile u32 VIDW01ADD2;

volatile u32 VIDW02ADD2;

volatile u32 VIDW03ADD2;

volatile u32 VIDW04ADD2;

volatile u8 res13[28];

volatile u32 VIDINTCON0;

volatile u32 VIDINTCON1;

volatile u8 res14[8];

volatile u32 W1KEYCON0;

volatile u32 W1KEYCON1;

volatile u32 W2KEYCON0;

volatile u32 W2KEYCON1;

volatile u32 W3KEYCON0;

volatile u32 W3KEYCON1;

volatile u32 W4KEYCON0;

volatile u32 W4KEYCON1;

volatile u8 res15[16];

volatile u32 DITHMODE;

volatile u8 res16[12];

volatile u32 WIN0MAP;

volatile u32 WIN1MAP;

volatile u32 WIN2MAP;

volatile u32 WIN3MAP;

volatile u32 WIN4MAP;

volatile u8 res17[12];

volatile u32 WPALCON;

volatile u32 TRIGCON;

volatile u32 ITUIFCON0;

volatile u8 res18[4];

volatile u32 I80IFCONA0;

volatile u32 I80IFCONA1;

volatile u32 I80IFCONB0;

volatile u32 I80IFCONB1;

volatile u8 res19[16];

volatile u32 LDI_CMDCON0;

volatile u32 LDI_CMDCON1;

volatile u8 res20[8];

volatile u32 SIFCCON0;

volatile u32 SIFCCON1;

volatile u32 SIFCCON2;

volatile u8 res21[148];

volatile u32 LDI_CMD0;

volatile u32 LDI_CMD1;

volatile u32 LDI_CMD2;

volatile u32 LDI_CMD3;

volatile u32 LDI_CMD4;

volatile u32 LDI_CMD5;

volatile u32 LDI_CMD6;

volatile u32 LDI_CMD7;

volatile u32 LDI_CMD8;

volatile u32 LDI_CMD9;

volatile u32 LDI_CMD10;

volatile u32 LDI_CMD11;

volatile u8 res22[80];

volatile u32 W2PDATA01;

volatile u32 W2PDATA23;

volatile u32 W2PDATA45;

volatile u32 W2PDATA67;

volatile u32 W2PDATA89;

volatile u32 W2PDATAAB;

volatile u32 W2PDATACD;

volatile u32 W2PDATAEF;

volatile u32 W3PDATA01;

volatile u32 W3PDATA23;

volatile u32 W3PDATA45;

volatile u32 W3PDATA67;

volatile u32 W3PDATA89;

volatile u32 W3PDATAAB;

volatile u32 W3PDATACD;

volatile u32 W3PDATAEF;

volatile u32 W4PDATA01;

volatile u32 W4PDATA23;

} s3c64xx_fb;

以上为lcd控制器的寄存器，通过为这个结构体赋值，来实现配置寄存器。

8、driver/video下新建s3c6410_fb.c

#include

#if defined(CONFIG_VIDEO_S3C64X0)

#include

#include "videomodes.h"

#include

* Export Graphic Device

GraphicDevice smi;

#define VIDEO_MEM_SIZE 0x200000 /*NEC 4.3 inches: 480x272x16bit = 0x3FC00 bytes */

//CPU: S3C6400@667MHz

// Fclk = 667MHz, Hclk = 133MHz, Pclk = 66MHz (ASYNC Mode)

//extern void board_video_init(GraphicDevice *pGD);

/*******************************************************************************

* Init video chip with common Linux graphic modes (lilo)

void *video_hw_init (void)

{

s3c64xx_fb * const fb = s3c64xx_get_base_fb();

GraphicDevice *pGD = (GraphicDevice *)&smi;

int videomode;

unsigned long t1, hsynch, vsynch;

char *penv;

int tmp, i, bits_per_pixel;

struct ctfb_res_modes *res_mode;

struct ctfb_res_modes var_mode;

int clkval;

// unsigned char videoout;

/* Search for video chip */

printf("Video: ");

tmp = 0;

videomode =CONFIG_SYS_DEFAULT_VIDEO_MODE;

/* get video mode via environment */

if ((penv = getenv ("videomode")) != NULL) {

/* deceide if it is a string */

if (penv[0] <= '9') {

videomode = (int) simple_strtoul (penv, NULL, 16);

tmp = 1;

}

} else {

tmp = 1;

}

if (tmp) {

/* parameter are vesa modes */

/* search params */

for (i = 0; i < VESA_MODES_COUNT; i++) {

if (vesa_modes[i].vesanr == videomode)

break;

}

if (i == VESA_MODES_COUNT) {

printf ("no VESA Mode found, switching to mode 0x%x ", CONFIG_SYS_DEFAULT_VIDEO_MODE);

i = 0;

}

res_mode =

(struct ctfb_res_modes *) &res_mode_init[vesa_modes[i].

resindex];

bits_per_pixel = vesa_modes[i].bits_per_pixel;

} else {

res_mode = (struct ctfb_res_modes *) &var_mode;

bits_per_pixel = video_get_params (res_mode, penv);

}

/* calculate hsynch and vsynch freq (info only) */

t1 = (res_mode->left_margin + res_mode->xres +

res_mode->right_margin + res_mode->hsync_len) / 8;

t1 *= 8;

t1 *= res_mode->pixclock;

t1 /= 1000;

hsynch = 1000000000L / t1;

t1 *=

(res_mode->upper_margin + res_mode->yres +

res_mode->lower_margin + res_mode->vsync_len);

t1 /= 1000;

vsynch = 1000000000L / t1;

/* fill in Graphic device struct */

sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres,

res_mode->yres, bits_per_pixel, (hsynch / 1000),

(vsynch / 1000));

printf ("%s\n", pGD->modeIdent);

pGD->winSizeX = res_mode->xres;

pGD->winSizeY = res_mode->yres;

pGD->plnSizeX = res_mode->xres;

pGD->plnSizeY = res_mode->yres;

//printf("videomode = %x;\ni = %d\npgd->winsizex = %d;pGD->winSizeY = %d;pGD->plnSizeX = %d;pGD->plnSizeY = %d;\nbits_per_pixel =%d\n ",videomode,i,pGD->winSizeX,pGD->winSizeY,pGD->plnSizeX,pGD->plnSizeY,bits_per_pixel);

switch (bits_per_pixel) {

case 8:

pGD->gdfBytesPP = 1;

pGD->gdfIndex = GDF__8BIT_INDEX;

break;

case 15:

pGD->gdfBytesPP = 2;

pGD->gdfIndex = GDF_15BIT_555RGB;

break;

case 16:

pGD->gdfBytesPP = 2;

pGD->gdfIndex = GDF_16BIT_565RGB;

break;

case 24:

pGD->gdfBytesPP = 3;

pGD->gdfIndex = GDF_24BIT_888RGB;

break;

}

#if 0

/* statically configure settings for debug*/

pGD->winSizeX = pGD->plnSizeX = 480;

pGD->winSizeY = pGD->plnSizeY = 272;

pGD->gdfBytesPP = 2;

pGD->gdfIndex = GDF_16BIT_565RGB;

#endif

pGD->frameAdrs = LCD_VIDEO_ADDR; //in config file :include/configs/mini6410.h

pGD->memSize = VIDEO_MEM_SIZE;

/* Clear video memory */

memset((void *)pGD->frameAdrs, 0x00, pGD->memSize);

board_video_init(pGD); //in board init file :board/samsung/mini6410/mini6410.c for gpio etc.

t1 = res_mode->pixclock;

t1 /= 1000;

t1 = 1000000000L / t1;

clkval = (CONFIG_SYS_VIDEO_VCLOCK_HZ / t1) - 1;

fb->VIDCON0 = ( VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |

VIDCON0_CLKVALUP | VIDCON0_CLKVAL_F(clkval)|

VIDCON0_CLKDIR | VIDCON0_CLKSEL_HCLK );

fb->VIDCON1 = ( VIDCON1_INV_VSYNC | VIDCON1_INV_HSYNC);

fb->VIDTCON0 = ( VIDTCON0_VBPD(res_mode->upper_margin) |

VIDTCON0_VFPD(res_mode->lower_margin) |

VIDTCON0_VSPW(res_mode->vsync_len) );

fb->VIDTCON1 = ( VIDTCON1_HBPD(res_mode->left_margin) |

VIDTCON1_HFPD(res_mode->right_margin) |

VIDTCON1_HSPW(res_mode->hsync_len));

fb->VIDTCON2 = (VIDTCON2_LINEVAL(pGD->winSizeY - 1) | VIDTCON2_HOZVAL(pGD->winSizeX - 1));

#if defined(LCD_VIDEO_BACKGROUND)

fb->WINCON0 = (WINCON0_BPPMODE_16BPP_565 | WINCONx_ENWIN | WINCONx_HAWSWP);

fb->VIDOSD0A = (VIDOSDxA_TOPLEFT_X(0) | VIDOSDxA_TOPLEFT_Y(0));

fb->VIDOSD0B = (VIDOSDxB_BOTRIGHT_X(pGD->winSizeX - 1) | VIDOSDxB_BOTRIGHT_Y(pGD->winSizeY - 1));

fb->VIDOSD0C = (pGD->winSizeY * pGD->winSizeX);

#endif

fb->WINCON1 = (WINCON1_BPPMODE_16BPP_565 | WINCONx_ENWIN | WINCONx_HAWSWP);

fb->VIDOSD1A = (VIDOSDxA_TOPLEFT_X(0) | VIDOSDxA_TOPLEFT_Y(0));

fb->VIDOSD1B = (VIDOSDxB_BOTRIGHT_X(pGD->winSizeX - 1) | VIDOSDxB_BOTRIGHT_Y(pGD->winSizeY - 1));

#if defined(LCD_VIDEO_BACKGROUND)

fb->VIDOSD1C = (VIDISD14C_ALPHA0_R(LCD_VIDEO_BACKGROUND_ALPHA) |

VIDISD14C_ALPHA0_G(LCD_VIDEO_BACKGROUND_ALPHA) |

VIDISD14C_ALPHA0_B(LCD_VIDEO_BACKGROUND_ALPHA) );

// fb->VIDOSD1C = (pGD->winSizeY * pGD->winSizeX)&0xffffff;

#endif

fb->VIDOSD1D = (pGD->winSizeY * pGD->winSizeX);

// fb->VIDOSD1D = (500 * 300);

#if defined(LCD_VIDEO_BACKGROUND)

/* config Display framebuffer addr for background*/

fb-> VIDW00ADD0B0 = LCD_VIDEO_BACKGROUND_ADDR;

/* This marks the end of the frame buffer. */

fb-> VIDW00ADD1B0 = (fb->VIDW00ADD0B0 &0xffffff) + (pGD->winSizeX+0) * pGD->winSizeY * 2;

fb-> VIDW00ADD2= ((pGD->winSizeX * 2) & 0x1fff);

#endif

/* config Display framebuffer addr for console*/

fb-> VIDW01ADD0B0 = pGD->frameAdrs;

/* This marks the end of the frame buffer. */

fb-> VIDW01ADD1B0 = (fb->VIDW01ADD0B0 &0xffffff) + (pGD->winSizeX+0) * pGD->winSizeY * 2;

fb-> VIDW01ADD2= ((pGD->winSizeX * 2) & 0x1fff);

/* Enable Display */

fb-> VIDCON0 |= (VIDCON0_ENVID | VIDCON0_ENVID_F); /* ENVID = 1 ENVID_F = 1*/

return ((void*)&smi);

}

void

video_set_lut (unsigned int index, /* color number */

unsigned char r, /* red */

unsigned char g, /* green */

unsigned char b /* blue */

)

{

}

//just init some reg for enable LCD

void board_video_init(GraphicDevice *pGD)

{

*(volatile unsigned long *)(0x7F008100) = 0xaaaaaaaa;//GPICON = 0xaaaaaaaa

*(volatile unsigned long *)(0x7F008108) = 0xaaaaaaaa;//GPIPUD = 0xaaaaaaaa

*(volatile unsigned long *)(0x7F008120) = 0xaaaaaaaa;//GPJCON = 0xaaaaaaaa

*(volatile unsigned long *)(0x7F008128) = 0xaaaaaaaa;//GPJPUD = 0xaaaaaaaa

*(volatile unsigned long *)(0x7F0081A0) &= ~(0x03);

*(volatile unsigned long *)(0x7F0081A0) |= 0x01;//特殊端口控制寄存器，选择LCD I/F 管脚组态为01=RGB I/F 形态。

*(volatile unsigned long *)(0x7410800C) &= ~(1<<3);//调制解调器接口端口控制寄存器（MIFPCON）的第三位SEL_BYPASS必须设这成0.

}

#endif /* CONFIG_VIDEO_S3C64X0 */

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