TITLE " TWO WIRE/I2C BUS INTERFACE WITH PIC16C5x "
;
LIST P=16C54
;
;*****************************************************************************
;** Two wire/I2C Bus READ/WRITE Sample Routines of Microchip's
;** 24Cxx / 85Cxx serial CMOS EEPROM interfacing to a
;** PIC16C54 8-bit CMOS single chip microcomputer
;** Revsied Version 2.0 (4/2/92).
;**
;** Part use = PIC16C54-XT/JW
;** Note: 1) All timings are based on a reference crystal frequency of 2MHz
;** which is equivalent to an instruction cycle time of 2 usec.
;** 2) Address and literal values are read in octal unless otherwise
;** specified.
;
;
; Program: I2CBUS.ASM
; Revision Date:
; 12-12-95 Compatibility with MPASMWIN 1.30
;
;**********************************************************************
;
;*****************************************************************************
;
;-----------------------------------------------------------------------------
; Files Assignment
;-----------------------------------------------------------------------------
;
PC EQU 2 ; Program counter
STAT EQU 3 ; PIC status byte
FSR EQU 4 ; File Select Register
RA EQU 5 ; Port A use to select device address
RB EQU 6 ; RB7 = SDA, RB6 = SCL
;
STATUS EQU 08 ; Status register
FLAG EQU 09 ; Common flag bits register
EEPROM EQU 0A ; Bit buffer
ERCODE EQU 0B ; Error code (to indicate bus status)
ADDR EQU 10 ; Address register
DATAI EQU 11 ; Stored data input register
DATAO EQU 12 ; Stored data output register
SLAVE EQU 13 ; Device address (1010xxx0)
TXBUF EQU 14 ; TX buffer
RXBUF EQU 15 ; RX buffer
COUNT EQU 16 ; Bit counter
;
TIMER0 EQU 18 ; Delay timer0
TIMER1 EQU 19 ; Delay timer1
;
;
;-----------------------------------------------------------------------------
; Bit Assignments
;-----------------------------------------------------------------------------
;
; Status bits
;
Z EQU 2
C EQU 0
;
; FLAG Bits
;
ERR1 EQU 0 ; Error flag
;
; Instruction Destination Bits
;
F EQU 1
W EQU 0
;
; EEPROM Bits
;
DI EQU 7 ; EEPROM input
DO EQU 6 ; EEPROM output
;
; I2C Device Bits
;
SDA EQU 7 ; RB7, data in/out
SCL EQU 6 ; RB6, serial clock
;
;END FILES/BITS EQUATE
PAGE
;
;-----------------------------------------------------------------------------
; Two wire/I2C - CPU communication error status table and subroutine
;-----------------------------------------------------------------------------
; input : W-reg = error code
; output : ERCODE = error code
; FLAG(ERR1) = 1
;
; code error status mode
; ------- ------------------------------------------------------
; 1 : SCL locked low by device (bus is still busy)
; 2 : SDA locked low by device (bus is still busy)
; 3 : No acknowledge from device (no handshake)
; 4 : SDA bus not released for master to generate STOP bit
;-----------------------------------------------------------------------------
;
;Subroutine to identify the status of the serial clock (SCL) and serial data
;(SDA) condition according to the error status table. Codes generated are
;useful for bus/device diagnosis.
;
ERR
BTFSS FLAG,ERR1 ; Remain as first error encountered
MOVWF ERCODE ; Save error code
BSF FLAG,ERR1 ; Set error flag
RETLW 0
;
;-----------------------------------------------------------------------------
; START bus communication routine
;-----------------------------------------------------------------------------
; input : none
; output : initialize bus communication
;-----------------------------------------------------------------------------
;
;Generate START bit (SCL is high while SDA goes from high to low transition)
;and check status of the serial clock.
BSTART
MOVLW B'00111111' ; Put SCL, SDA line in output state
TRIS RB
;***************************************************************************
bsf RB,SDA ;make sure sda is high
;***************************************************************************
BSF RB,SCL ; Set clock high
MOVLW 1 ; Ready error status code 1
BTFSS RB,SCL ; Locked?
CALL ERR ; SCL locked low by device
BCF RB,SDA ; SDA goes low during SCL high
NOP ; Timing adjustment
NOP
NOP
BCF RB,SCL ; Start clock train
RETLW 0
;
;END SUB
PAGE
;
;-----------------------------------------------------------------------------
; STOP bus communication routine
;-----------------------------------------------------------------------------
; Input : None
; Output : Bus communication, STOP condition
;-----------------------------------------------------------------------------
;
;Generate STOP bit (SDA goes from low to high during SCL high state)
;and check bus conditions.
;
BSTOP
;****************************************************************************
MOVLW B'00111111' ; Put SCL, SDA line in output state
TRIS RB
;****************************************************************************
BCF RB,SDA ; Return SDA to low
BSF RB,SCL ; Set SCL high
nop
nop
nop
MOVLW 1 ; Ready error code 1
BTFSS RB,SCL ; High?
CALL ERR ; No, SCL locked low by device
BSF RB,SDA ; SDA goes from low to high during SCL high
MOVLW 4 ; Ready error code 4
BTFSS RB,SDA ; High?
CALL ERR ; No, SDA bus not release for STOP
RETLW 0
;
;END SUB
;
;-----------------------------------------------------------------------------
; Serial data send from PIC to serial EEPROM, bit-by-bit subroutine
;-----------------------------------------------------------------------------
; Input
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