例程序：

//******************************************************************************
//  MSP-FET430P140 Demo - Timer_A, Toggle P1.1/TA0, Up Mode, DCO SMCLK
//
//  Description: Toggle P1.1 using hardware TA0 output. Timer_A is configured
//  for up mode with CCR0 defining period, TA0 also output on P1.1. In this
//  example, CCR0 is loaded with 500-1 and TA0 will toggle P1.1 at TACLK/500.
//  Thus the output frequency on P1.1 will be the TACLK/1000. No CPU or
//  software resources required.
//  As coded with TACLK = SMCLK, P1.1 output frequency is ~800000/1000.
//  SMCLK = MCLK = TACLK = default DCO ~800kHz
//
//           MSP430F149
//         -----------------
//     /||              XIN|-
//      | |                 |
//      --|RST          XOUT|-
//        |                 |
//        |         P1.1/TA0|--> SMCLK/1000
//
//  M. Buccini
//  Texas Instruments Inc.
//  Feb 2005
//  Built with IAR Embedded Workbench Version: 3.21A
//修改时间:2008.8.20 am 8:13
// only timera 依靠DCO工作，而CPU 停止工作。
//******************************************************************************

#include 

void main(void)
{
  WDTCTL = WDTPW + WDTHOLD;                 // Stop WDT
  P1DIR |= 0x02;                            // P1.1 output
  P1SEL |= 0x02;                            // P1.1 option select
  CCTL0 = OUTMOD_4;                         // CCR0 toggle mode
  CCR0 = 500-1;
  TACTL = TASSEL_2 + MC_1;                  // SMCLK, upmode

  _BIS_SR(CPUOFF);                          // CPU off
}

//******************************************************************************
//  MSP-FET430P140 Demo - Timer_A, Toggle P1.1/TA0, Up/Down Mode, 32kHz ACLK
//
//  Description: Toggle P1.1 using hardware TA0 output. Timer_A is configured
//  for up/down mode with CCR0 defining period, TA0 also output on P1.1. In
//  this example, CCR0 is loaded with 5 and TA0 will toggle P1.1 at TACLK/2*5.
//  Thus the output frequency on P1.1 will be the TACLK/20. No CPU or software

此处的说明与DATASHEET中的图不符合，并且DATASHEET中的图不是太懂
//  resources required. Normal operating mode is LPM3.
//  As coded with TACLK = ACLK, P1.1 output frequency = 32768/20 = 1.6384kHz
//  ACLK = TACLK = 32kHz, MCLK = default DCO ~800kHz
//  //* External watch crystal installed on XIN XOUT is required for ACLK *// 
//
//              MSP430F149
//            -----------------
//        /||              XIN|-
//         | |                 | 32kHz
//         --|RST          XOUT|-
//           |                 |
//           |             P1.1|-->TA0 ACLK/20
//
//  M. Buccini
//  Texas Instruments Inc.
//  Feb 2005
//  Built with IAR Embedded Workbench Version: 3.21A
//******************************************************************************

#include 

void main(void)
{
  WDTCTL = WDTPW + WDTHOLD;                 // Stop WDT
  P1DIR |= 0x02;                            // P1.1 output
  P1SEL |= 0x02;                            // P1.1 option select
  CCTL0 = OUTMOD_4;                         // CCR0 toggle mode
  CCR0 = 5;
  TACTL = TASSEL_1 + MC_3;                  // ACLK, up-downmode

  _BIS_SR(LPM3_bits);                       // Enter LPM3
}