// 时钟默认情况  

// FLL时钟      FLL选择 XT1  

// 辅助时钟     ACLK选择 XT1          32768Hz  

// 主系统时钟   MCLK选择 DCOCLKDIV    8000000Hz  

// 子系统时钟   SMCLK选择 DCOCLKDIV   8000000Hz  

// TA1选择ACLK，最大计数值为16384，中断频率为2HZ  

// 在TIMER1_A0_VECTOR中翻转P4.0  

#include   

#include   

void clock_config(void);  

void select_xt1(void);  

void dco_config(void);  

int main(void)  

{  

    clock_config();                             // 初始化时钟  

    P4DIR |= BIT0;                              // P4.0输出  

    TA1CCTL0 = CCIE;                            // 使能TA1CCR0，比较匹配中断  

    TA1CCR0 = 16384;                            // 初始化最大值,发生比较匹配中断频率 32768/16384 = 2Hz  

    TA1CTL = TASSEL_1 + MC_1 + TACLR;           // 选择ACLK，最大值为CCR0，清除计数值  

    _EINT();                                    // 初始化全局中断  

    while(1)  

    {  

        ;  

    }  

}  

void clock_config(void)  

{  

    WDTCTL = WDTPW + WDTHOLD;                   // 停止看门狗  

    select_xt1();                               // 选择XT1  

    dco_config();                               // ACLK = XT1 = 32.768K  

                                                // MCLK = SMCLK = 8000K  

}  

void select_xt1(void)  

{  

    // 启动XT1  

    P7SEL |= 0x03;                              // P7.0 P7.1 外设功能  

    UCSCTL6 &= ~(XT1OFF);                       // XT1打开  

    UCSCTL6 |= XCAP_3;                          // 内部电容  

    do  

    {  

        UCSCTL7 &= ~XT1LFOFFG;                  // 清楚XT1错误标记  

    }while (UCSCTL7&XT1LFOFFG);                 // 检测XT1错误标记  

}  

void dco_config(void)  

{  

    __bis_SR_register(SCG0);                    // 禁止FLL功能  

    UCSCTL0 = 0x0000;                           // Set lowest possible DCOx, MODx  

    UCSCTL1 = DCORSEL_5;                        // DCO最大频率为16MHz  

    UCSCTL2 = FLLD_1 + 243;                     // 设置DCO频率为8MHz  

                                                // MCLK = SMCLK= Fdcoclkdiv = (N+1)X(Ffllrefclk/n)  

                                                // N为唯一需要计算的值  

                                                // Ffllrefclk FLL参考时钟，默认为XT1  

                                                // n取默认值，此时为1  

                                                // (243 + 1) * 32768 = 8MHz  

    __bic_SR_register(SCG0);                    // 使能FLL功能  

    // 必要延时  

    __delay_cycles(250000);  

    // 清楚错误标志位  

    do  

    {  

        UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);  

                                                // 清除所有振荡器错误标志位  

        SFRIFG1 &= ~OFIFG;                      // 清除振荡器错误  

    }while (SFRIFG1&OFIFG);                     // 等待清楚完成  

}  

#pragma vector=TIMER1_A0_VECTOR  

__interrupt void TIMER1_A0_ISR(void)  

{  

    P4OUT ^= BIT0;  

}