1.中断向量表

每个中断都对应一段中断服务程序。当中断发生时，处理器就执行该中断对应的服务程序，实现该中断所要求完成的任务。处理器如何找到对应的中断服务程序呢？这就需要读取处理器的中断向量表。

中断向量表其实就对应了系统的一段存储区，它按照一定规律存储了处理器中所有不同类型中断的服务程序入口地址（又称中断向量）。S3C2410是基于ARM920T核，ARM920T的中断向量表有两种存放方式，一种是低端存放（从0x00000000处开始存放），另一种是高端存放（从0xfff000000处开始存放）。ARM920T能处理8个类型的中断，他们分别是：

>Reset：当处理器的复位电平有效时，产生复位异常，程序跳转到复位处理程序执行。

>Undefined instruction：当处理器遇到不能处理的指令时产生未定义指令中断。

>Software Interrupt：执行SWI（软件中断）指令时产生，可用于用户实现系统调用

>Abort (prefetch)：当处理器预取指令的地址不存在或该地址不允许当前指令访问时，存储器会向处理器发出中止信号，但当预取的指令被执行时，才会产生指令预取中断。

>Abort (data)：当处理器访问的指令地址不存在或该地址不允许当前指令访问时，产生数据中止中断。

>Reserved：保留。

>IRQ：当处理器的外部中断请求引脚有效，且CPSR的I位为0时产生IRQ中断。

>FIQ：当处理器的快速中断请求引脚有效，且CPSR的F位为0时产生FIQ中断。

对应的中断向量表如表1-1所示。

表1-1中断向量表

一般情况下，在每个入口地址处都存放了一条跳转指令，我们知道Uboot是用来完成系统的启动加载过程的，在u-boot的/cpu/start.S文件中，就有“b reset”指令，放在0x00000000地址。系统上电以后，CPU将会从0x00000000处得这条指令执行，执行完以后，CPU会跳转到reset标识的代码段去执行处理器复位程序。同样，在系统运行过程中，每当有中断发生，CPU会根据中断类型（用中断号标识），从内存的0x00000000处开始查表做相应的处理。比如系统触发了一个IRQ中断，IRQ为第6号中断，则CPU将把PC指向0x00000018地址（4*6=24= 0x00000018）处运行，该地址的指令是跳转到“IRQ中断服务程序”处运行。

S3C2410中断源，如图1-1中断源所示：

图1-1中断源

INTERRUPT CONTROLLER OPERATION

F-bit and I-bit of Program Status Register (PSR)

If the F-bit of PSR in ARM920T CPU is set to 1, the CPU does not accept the Fast Interrupt Request (FIQ) from the interrupt controller. Likewise, If I-bit of the PSR is set to 1, the CPU does not accept the Interrupt Request (IRQ) from the interrupt controller. So, the interrupt controller can receive interrupts by clearing F-bit or I-bit of the PSR to 0 and setting the corresponding bit of INTMSK to 0.

Interrupt Mode

The ARM920T has two types of Interrupt mode: FIQ or IRQ. All the interrupt sources determine which mode is used at interrupt request.

Interrupt Pending Register

The S3C2410A has two interrupt pending resisters: source pending register (SRCPND) and interrupt pending register (INTPND). These pending registers indicate whether or not an interrupt request is pending. When the interrupt sources request interrupt service, the corresponding bits of SRCPND register are set to 1, and at the same time, only one bit of the INTPND register is set to 1 automatically after arbitration procedure. If interrupts are masked, the corresponding bits of the SRCPND register are set to 1. This does not cause the bit of INTPND register changed. When a pending bit of the INTPND register is set, the interrupt service routine starts whenever the I-flag or F-flag is cleared to 0. The SRCPND and INTPND registers can be read and written, so the service routine must clear the pending condition by writing a 1 to the corresponding bit in the SRCPND register first and then clear the pending condition in the INTPND registers by using the same method.

Interrupt Mask Register

This register indicates that an interrupt has been disabled if the corresponding mask bit is set to 1. If an interrupt mask bit of INTMSK is 0, the interrupt will be serviced normally. If the corresponding mask bit is 1 and the interrupt is generated, the source pending bit will be set.

S3C2410的中断控制器原理如图1-2所示。

图1-2中断控制器原理

由上图可以看出S3C2410的中断控制器主要通过几个控制寄存器来实现：中断源待决寄存器（Source Pending Register，SRCPND/SUBSRCPND）、中断模式寄存器（Interrupt Mode Register,INTMOD）、中断屏蔽寄存器（Interrupt Mask Register,INTMASK/INTSUBMSK）、中断优先级控制寄存器（IRQ PRIORITY Control Register,PRIORITY）、中断待决寄存器（Interrupt Pending Register,INTPND）。

该图也显示了S3C2410的中断处理流程：首先要有中断源产生中断，这里面有两条路径表示中断源，上面一条是次级中断源，当次级中断产生后，首先在SUBSRCPND寄存器中登记，然后经过次级屏蔽寄存器（SUBMASK）来决定这个次级中断源所产生的中断是否被屏蔽掉，被屏蔽掉的中断将不会被执行。次级中断源所产生的中断在经过SUBMASK之后将会与主中断源所产生的中断汇合，然后在SRCPND寄存器中登记，再经过主屏蔽寄存器，得出该中断是否被送往CPU处理的决定。当然，在送往CPU处理之前，还要根据中断模式寄存器的设置判断一下该中断是属于IRQ中断还是FIQ中断，如果是FIQ中断则直接触发。如果是IRQ中断，则还要判断中断的优先级别，级别高的先执行。

（1）中断源待决寄存器SRCPND/ SUBSRCPND

这两个寄存器在功能上是相同的，它们是中断源待决寄存器。在一个中断处理流程中，中断信号传进中断控制器后首先遇到的就是SRCPND/ SUBSRCPND,这两个寄存器的作用是用于标示出哪个中断请求被触发。SRCPND的有效位为32，SUBSRCPND的有效位为11，它们中的每一位分别代表一个中断源。SRCPND为主中断源待决寄存器，SUBSRCPND为次中断源待决寄存器。

The SRCPND register is composed of 32 bits each of which is related to an interrupt source. Each bit is set to 1 if the corresponding interrupt source generates the interrupt request and waits for the interrupt to be serviced. Accordingly, this register indicates which interrupt source is waiting for the request to be serviced. Note that each bit of the SRCPND register is automatically set by the interrupt sources regardless of the masking bits in the INTMASK register. In addition, the SRCPND register is not affected by the priority logic of interrupt controller.

In the interrupt service routine for a specific interrupt source, the corresponding bit of the SRCPND register has to be cleared to get the interrupt request from the same source correctly. If you return from the ISR without clearing the bit, the interrupt controller operates as if another interrupt request came in from the same source. In other words, if a specific bit of the SRCPND register is set to 1, it is always considered as a valid interrupt request waiting to be serviced.

The time to clear the corresponding bit depends on the users requirement. If you want to receive another valid request from the same source, you should clear the corresponding bit first, and then enable the interrupt.

You can clear a specific bit of the SRCPND register by writing a data to this register.It clears only the bit positions of the SRCPND corresponding to those set to one in the data. The bit positions corresponding tothose that are set to 0 in the data remains as they are.

SRCPND的各个位信息如表1-3所示。

表1-3 SRCPND各位信息

SRCPN寄存器中每个位的初始值皆为0。假设现在系统触发了EINT0中断，则第0位将被置1，代表EINT0中断被触发，该中断请求即将被处理（若该中断没有被屏蔽的话）。SUBSRCPND情况与SRCPND相同，如表1-4所示。

表1-4 SUBSRCPND各位信息

（2）中断模式寄存器INTMOD

该寄存器用来指定中断源处理模式（IRQ还是FIQ），有效位为32位，每一位与SRCPND中各位相对应，若某位为0，则该位相对应的中断按IRQ模式处理，为1则以FIQ模式进行处理，该寄存器初始化值为0x00000000,即所有中断皆以IRQ模式进行处理。如表1-5所示。

This register is composed of 32 bits each of which is related to an interrupt source. If a specific bit is set to 1, the corresponding interrupt is processed in the FIQ (fast interrupt) mode. Otherwise, it is processed in the IRQ mode (normal interrupt).

Note that only one interrupt source can be serviced in the FIQ mode in the interrupt controller (you should use the FIQ mode only for the urgent interrupt). Thus,only one bit of INTMOD can be set to 1.

表1-5 INTMOD寄存器

NOTE: If an interrupt mode is set to FIQ mode in the INTMOD register, FIQ interrupt will not affect both INTPND and INTOFFSET registers. In this case, the two registers are valid only for IRQ mode interrupt source.

（3）中断屏蔽寄存器INTMSK/ INTSUBMSK

This register also has 32 bits each of which is related to an interrupt source. If a specific bit is set to 1, the CPU does not service the interrupt request from the corresponding interrupt source (note that even in such a case, the corresponding bit of SRCPND register is set to 1). If the mask bit is 0, the interrupt request can be serviced.

INTMSK为主中断屏蔽寄存器，INTSUBMSK为次中断屏蔽寄存器。INTMSK有效位为32，INTSUBMSK有效位为11，这两个寄存器各个位与SRCPND和SUBSRCPND分别对应。它们的作用是决定该位相应的中断请求是否被处理。若某位被设置为1，则该位相对应的中断产生后将被忽略（CPU不处理该中断请求），设置为0则对其进行处理。这两个寄存器初始化后的值是0xFFFFFFFF和0x7FF，既默认情况下所有的中断都是被屏蔽的。如表1-6所示。

表1-6INTMSK寄存器

（4）PRIORITY寄存器

一个嵌入式系统一般有多个中断请求源。当多个中断源同时请求中断时，就会存在CPU应该优先响应哪个中断请求源的问题，如果处理不当将会引起混乱，导致系统不能正常工作。通常解决这个问题的方法是根据中断源事件的轻重缓急规定中断源的优先级，CPU优先响应中断优先级高的中断请求。

S3C2410的优先级判断分为两级。如图1-3所示，SRCPND寄存器对应的32个中断源总共被分为6个组，每个组由一个ARBITER（0~5）寄存器对其进行管理。中断必须先由所属组的ARBITER（0~5）进行第一次优先级判断（第一级判断）后再发往ARBITER6进行最终的判断（第二级判断）。ARBITER（0~5）这六个组的优先级已经固定，由ARBITER0控制的组优先级最高，其次是ARBITER1, ARBITER2, ARBITER3, ARBITER4, ARBITER5。但是每个组中的各个中断的优先级是可以控制的，我们只需要设置PRIORITY的相应位。

图1-3 Priority Generating Block

INTERRUPT PRIORITY

Each arbiter can handle six interrupt requests based on the one bit arbiter mode control (ARB_MODE) and two bits of selection control signals (ARB_SEL) as follows:

— If ARB_SEL bits are 00b, the priority order is REQ0, REQ1, REQ2, REQ3, REQ4, and REQ5.

— If ARB_SEL bits are 01b, the priority order is REQ0, REQ2, REQ3, REQ4, REQ1, and REQ5.

— If ARB_SEL bits are 10b, the priority order is REQ0, REQ3, REQ4, REQ1, REQ2, and REQ5.

— If ARB_SEL bits are 11b, the priority order is REQ0, REQ4, REQ1, REQ2, REQ3, and REQ5.

Note that REQ0 of an arbiter always has the highest priority, and REQ5 has the lowest one. In addition, by changing the ARB_SEL bits, we can rotate the priority of REQ1 to REQ4.

Here,if ARB_MODE bit is set to 0, ARB_SEL bits are not automatically changed, making the arbiter to operate in the fixed priority mode (note that even in this mode, we can reconfigure the priority by manually changing the ARB_SEL bits). On the other hand, if ARB_MODE bit is 1, ARB_SEL bits are changed in rotation fashion, e.g., if REQ1 is serviced, ARB_SEL bits are changed to 01b automatically so as to put REQ1 into the lowest priority. The detailed rules of ARB_SEL change are as follows:

— If REQ0 or REQ5 is serviced, ARB_SEL bits are not changed at all.

— If REQ1 is serviced, ARB_SEL bits are changed to 01b.

— If REQ2 is serviced, ARB_SEL bits are changed to 10b.

— If REQ3 is serviced, ARB_SEL bits are changed to 11b.

— If REQ4 is serviced, ARB_SEL bits are changed to 00b.

表1-7 PRIORITY寄存器

表1-7是PRIORITY寄存器各个位的参数表。从表上我们可以知道PRIORITY寄存器内部各个位被分为两种类型，一种是ARB_MODE,另一种为ARB_SEL, ARB_MODE类型有5组，分别对应ARBITER（2~6），ARB_SEL类型有7组，分别对应ARBITER（0~6）。

以ARBITER2为例，我们来看一下PRIORITY寄存器中ARB_SEL, ARB_MODE之间的相互关系。首先我们看到ARBITER2寄存器管理的该组中断里包括了6个中断，分别是INT_TIMER0，INT_TIMER1，INT_TIMER2，INT_TIMER3，INT_TIMER4，INT_UART2，它们的默认中断请求号分别为REQ0，REQ1，REQ2，REQ3，REQ4，REQ5。我们先看PRIORITY寄存器中的ARB_SEL2，该参数由两个位组成，初始值为00。从该表可以看出00定义了一个顺序0-1-2-3-4-5，这个顺序就是这组中断组的优先级排列，这个顺序指明了以中断请求号为0（REQ0）的INT_TIMER0具有最高的中断优先级，其次是INT_TIMER1，INT_TIMER2…。假设现在ARB_SEL2的值被我们设置为01。则一个新的优先级次序将被使用，01对应的优先级次序为0-2-3-4-1-5，从中可以看出优先级最高和最低的中断请求和之前没有变化，但本来处于第2优先级的INT_TIMER1中断现在变成了第5优先级。从ARB_SEL2被设置为00,01,10,11各个值所出现的情况可以看出，除了最高和最低的优先级不变以外，其他各个中断的优先级其实是在做一个旋转排列（rotate）。为了达到对各个中断平等对待这一目标，我们可以让优先级次序在每个中断请求被处理完之后自动进行一次旋转，如何自动让它旋转呢？我们可以通过设置ARB_MODE2位达到这个目的，该位置1代表开启对应中断组的优先级次序自动旋转，0则为关闭，按固定的次序排列优先级列表。

（5）中断待决寄存器INTPND

Each of the 32 bits in the interrupt pending register shows whether the corresponding interrupt request, which is unmasked and waits for the interrupt to be serviced, has the highest priority .Since the INTPND register is located after the priority logic, only one bit can be set to 1, and that interrupt request generates IRQ to CPU.In interrupt service routine for IRQ, you can read this register to determine which interrupt source is serviced among the 32 sources.

Like the SRCPND register,this register has to be cleared in the interrupt service routine after clearing the SRCPND register. We can clear a specific bit of the INTPND register by writing a data to this register.It clears only the bit positions of the INTPND register corresponding to those set to one in the data. The bit positions corresponding to those that are set to 0 in the data remains as they are.

INTPND的详细信息如表1-8所示：

表1-8寄存器INTPND

表1-8是INTPND寄存器各位的详细功能列表。不难发现，INTPND寄存器与SRCPND长得一模一样，但他们在中断处理中却扮演着不同的角色。INTPND寄存器的每个位对应一个中断请求，若该位被置1，则表示相应的中断请求被触发。说到这里你可能会发现它不仅和SRCPND长得一模一样，就连功能都一样，其实不然，他们在功能上有着重大的区别。SRCPND是中断源待决寄存器，某个位被置1表示相应的中断被触发，但我们知道在同一时刻内系统可以触发若干个中断，只要中断被触发了，SRCPND的相应位便被置1，也就是说SRCPND在同一时刻可以有若干位同时被置1，然而INTPND则不同，他在某一时刻只能有1个位被置1，INTPND某个位被置1，则表示CPU即将或已经在对该位相应的中断进行处理。于是我们可以有一个总结：SRCPND说明了有什么中断被触发了，INTPND说明了CPU即将或已经在对某一个中断进行处理。

每当某一个中断被处理完之后，我们必须手动将SRCPND/SUBSRCPND , INTPND三个寄存器中与该中断相应的位由1设置为0。

（6）中断偏移寄存器INTOFFSET

INTOFFSET寄存器的功能很简单，它用于表明哪个中断正在被处理。表1-9是该寄存器各位详细功能列表：若当前INT_TIMER0被触发了，则该寄存器的值为10，以此类推。

表1-9 INTOFFSET寄存器