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设计基于LED的视频显示板 Designing an LED-Based Video-Display Board
Abstract: Currently, all of the top LED video-display board manufacturers have similar but proprietary architectures using LED video bricks of different color pixel sizes. Maxim has taken its knowledge of these applications and incorporated the unique features of the MAX6974 LED driver into a reference design for an LED-based video-display board that is used with a low-cost, medium-size FPGA chip.
Introduction
Roughly tens of thousands of large-size LED video-display boards have been installed worldwide. The adoption of LED video display boards can become even more widespread if the overall system price can be significantly reduced and the operational procedure of such display boards can be simplified. The following application note represents a reference design for a basic, low-cost, modular LED video-display board. The design's new architecture uses a combination of one inexpensive FPGA chip for the digital video bit stream demultiplexing and the features of MAX6974 LED drivers to build a QVGA (320 x 240) resolution LED video display. This display board can be controlled by a PC and used as a secondary monitor to display any text, graphic, or multimedia information.Current LED Video-Display Board Architecture
Currently, all of the top LED video-display board manufacturers have similar but proprietary architectures using LED video bricks of different color pixel sizes. The video-brick pixel size ranges from 256 to 15552, depending on the manufacturer. The video bricks can be put next to each other to assemble a video wall of a few meters in size on each side (Figure 1). LEDs and their drivers are mounted close to each other on different PCBs inside each video brick. Also included on the LED-driver PCB are an FPGA and video-buffer memory chips.For a video wall, interconnections between video bricks are normally made using coaxial cables. The video wall is then linked to control and video processing units by optical fiber. The control unit is used to configure these video bricks and select the proper video source. The video processor receives the selected video signal, converts its format, and sends the correct data information to the corresponding pixel position. Data buffering and scaling are also tasks completed by the video processor. The application's controller and video processor units are specialized professional equipment that can be very expensive.
Figure 1. Today's LED video-display board system architecture.
Maxim's Approach
Using the unique features of the MAX6974 LED driver, an LED video-display board can be constructed with the help of a low-cost, medium-size FPGA chip. The entire system is controlled by a PC (Figure 2). With the addition of a video-interface PC card, different video-signal sources can all be accommodated. The result is a complete LED video-display board with fewer electronics components and no need for specialized operational equipment.More detailed image (PDF, 12kB)
Figure 2. MAX6974-based LED video-display board system architecture.
MAX6974 LED Driver Features
The MAX6974 LED driver is designed specifically for LED video-display board applications. Each LED driver has 24 coordinated, constant-current, PWM LED driver ports and can drive eight or 16 (duplex mode) RGB pixels. To accommodate video or still camera pictures without the outcome being a blank screen, the PWM rate of this chip is very fast. At a video refresh rate of 60fps (frames per second), the PWM rate is about 7680Hz. The MAX6974's data-input interface consists of one LVDS clock and LVDS data pairs. Data bits intended for additional serialized MAX6974 LED drivers are available through a data-output interface, which also includes an LVDS clock and a LVDS data pairs. Depending on the video refresh rate and the clock frequency, hundreds of MAX6974 devices can be linked together through the LVDS interface. Because of this interface, interconnections between the LED drivers and the video-display module PCBs can be made through twisted-pair cables of up to a few feet.The intensity of each LED can be controlled in three ways by the MAX6974. First, each individual LED (red, green, or blue) has a PWM intensity control of 12 bits. That is much more than the 8-bit per color resolution defined by the DVI™ interface. The extra bits may be used for contrast adjustments to accommodate different ambient lighting conditions. Secondly, there are 7 bits of PDM intensity control affecting all LED drive ports. These PDM bits can be used for brightness control. Last, there are 256 (6mA to 30mA) steps of constant-current control for each color group of LED drive ports. These calibration steps can be used to match the desired video color temperature.
Detailing a MAX6974-Based LED Video-Display Board Architecture
This LED video-display board reference design uses a single FPGA chip to demultiplex video data bits. It also captures control frames and directly forwards them into corresponding registers inside each MAX6974 LED driver.Figure 3shows the functional block diagram of this reference design with QVGA resolution (320 x 240) using a TFP401A DVI receiver, an AT24C02 EEPROM to store an EDID, an EP2C20 FPGA, and 9600 MAX6974 LED drivers to drive 76,800 OVSRRGBCC3 RGB LEDs.More detailed image (PDF, 68kB)
Figure 3. Reference design functional block diagram.
The DVI signal on the left side of the block diagram is received by the TFP401A DVI receiver. The AT24C02 EEPROM is used to provide an EDID for the Windows® operating system. The deserialized and TMDS-decoded signal is then sent to the EP2C20. Reformatted video bits are made available to columns of the LED display module PCBs through 5 LVDS channels at a speed of about 32Mbps. An LVDS channel consists of 2 differential pairs, CLKI(O)±, DIN(OUT)±, a LOADI(O) pin, and a GND (ground) pin, for a total of 6 wires. Each LED display module PCB contains 64 MAX6974 LED drivers and 512 OVSRRGBCC3 RGB LEDs.
Video Bit Stream Demultiplexing and Control Video Frame
The lowest resolution for DVI is VGA. For the QVGA application of this reference design, only odd or even pixels and every other line are used. The half pixel clock rate from the TFP401A DVI receiver is 12.5MHz. The blanking overhead is approximately 40%. By taking only odd or even lines and purging the blanking overhead that is not required for the MAX6974's LVDS interface, the serialized (24-bit RGB) QVGA data rate is 12.5/2/1.4 × 24 = 107.142857Mbps. The effective data rate, considering DVI's 8-bit per color conversion to the MAX6974's 12-bit per color conversion, is107.142857/8 × 12 = 160.714286Mbps.The FPGA buffers the pixel data stream from the TFP401A DVI receiver, separates it into five groups, and sends them to their corresponding LVDS channels. The data rate at each LVDS channel is160.714286/5 = 32.1428571Mbps.Each pixel is de
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