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先安装ADS1.2，该软件主要用来编译并调试ARM处理器的程序的。下面所有的源程序都将通过ADS编译并最终链接成可执行文件，即.bin文件。
下面的程序主要是先初始化SDRAM，然后将程序跳转到SDRAM中，并点亮4个LED灯。
在ARM处理器启动的最开始，一般都需要：
1、关闭“看门狗”；
2、关闭中断；
然后再初始化SDRAM，因为在初始化SDRAM时，要用到时钟频率，所以也需要设置时钟频率。
以下是用汇编语言写的起动代码，为后面的C语言环境作铺垫。
WTCON EQU 0x53000000 ;Watch-dog timer mode
INTMSK EQU 0x4a000008 ;Interrupt mask control
INTSUBMSK EQU 0x4a00001c ;Interrupt sub mask
CLKDIVN EQU 0x4c000014 ;Clock divider control
LOCKTIME EQU 0x4c000000 ;PLL lock time counter
MPLLCON EQU 0x4c000004 ;MPLL Control
BWSCON EQU 0x48000000 ;Bus width & wait status
GPBCON EQU 0x56000010 ;Port B control
GPBDAT EQU 0x56000014 ;Port B data
M_MDIV EQU 92
M_PDIV EQU 1
M_SDIV EQU 1
_STACK_BASEADDRESS EQU 0x33ff8000
_MMUTT_STARTADDRESS EQU 0x33ff8000
_ISR_STARTADDRESS EQU 0x33ffff00
USERMODE EQU 0x10
FIQMODE EQU 0x11
IRQMODE EQU 0x12
SVCMODE EQU 0x13
ABORTMODE EQU 0x17
UNDEFMODE EQU 0x1b
MODEMASK EQU 0x1f
NOINT EQU 0xc0
UserStack EQU (_STACK_BASEADDRESS-0x3800) ;0x33ff4800 ~
SVCStack EQU (_STACK_BASEADDRESS-0x2800) ;0x33ff5800 ~
UndefStack EQU (_STACK_BASEADDRESS-0x2400) ;0x33ff5c00 ~
AbortStack EQU (_STACK_BASEADDRESS-0x2000) ;0x33ff6000 ~
IRQStack EQU (_STACK_BASEADDRESS-0x1000) ;0x33ff7000 ~
FIQStack EQU (_STACK_BASEADDRESS-0x0) ;0x33ff8000 ~
IMPORT |Image$$RO$$Base| ; Base of ROM code
IMPORT |Image$$RO$$Limit| ; End of ROM code (=start of ROM data)
IMPORT |Image$$RW$$Base| ; Base of RAM to initialise
IMPORT |Image$$ZI$$Base| ; Base and limit of area
IMPORT |Image$$ZI$$Limit| ; to zero initialise
IMPORT Main ; The main entry of mon program
AREA Init,CODE,READONLY
ENTRY
ResetEntry
;===============================
;关闭看门狗
;===============================
ldr r0, =WTCON
mov r1, #0x0
str r1, [r0]
;===============================
;关闭所有的中断
;===============================
ldr r0, =INTMSK
ldr r1, =0xffffffff
str r1, [r0]
;===============================
;关闭所有的子中断
;===============================
ldr r0, =INTSUBMSK
ldr r1, =0x7fff
str r1, [r0]
;===============================
;设置FCLK:HCLK:PCLK = 1:4:8
;===============================
ldr r0, =CLKDIVN
mov r1, #5
str r1, [r0]
;===============================
;设置异步总线模式
;===============================
mrc p15, 0, r1, c1, c0, 0
orr r1, r1, #0xc0000000
mcr p15, 0, r1, c1, c0, 0
;===============================
;设置锁存时间
;===============================
ldr r0, =LOCKTIME
ldr r1, =0xffffffff
str r1, [r0]
;===============================
;设置MPLL
;===============================
ldr r0, =MPLLCON
ldr r1, =((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV)
str r1, [r0]
;===============================
;Set memory control registers
;===============================
adrl r0, SMRDATA
ldr r1, =BWSCON
add r2, r0, #52
0
ldr r3, [r0], #4
str r3, [r1], #4
cmp r2, r0
bne %B0
;===============================
;点亮一个led灯GPB5
;===============================
ldr r0, =GPBCON
ldr r1, =0x00000400
str r1, [r0]
ldr r0, =GPBDAT
ldr r1, =0x00000000
str r1, [r0]
;===============================
;Clear SDRAM
;===============================
; mov r1,#0
; mov r2,#0
; mov r3,#0
; mov r4,#0
; mov r5,#0
; mov r6,#0
; mov r7,#0
; mov r8,#0
; ldr r9,=0x4000000 ;64MB
; ldr r0,=0x30000000
;0
; stmia r0!,{r1-r8}
; subs r9,r9,#32
; bne %B0
;===============================
;Initialize stacks
;===============================
bl InitStacks
;===============================
;从nor flash启动
;===============================
ldr r0, =BWSCON
ldr r0, [r0]
ands r0, r0, #6 ;OM[1:0] != 0, NOR FLash boot
bne copy_proc_beg
copy_proc_beg
;===============================
;点亮一个led灯GPB6
;===============================
ldr r0, =GPBCON
ldr r1, =0x00001400
str r1, [r0]
;===============================
;复制程序到SDRAM中
;===============================
adr r0, ResetEntry
ldr r2, BaseOfROM
cmp r0, r2
ldreq r0, TopOfROM
beq InitRam
ldr r3, TopOfROM
0
ldmia r0!, {r4-r7}
stmia r2!, {r4-r7}
cmp r2, r3
bcc %B0
sub r2, r2, r3
sub r0, r0, r2
InitRam
ldr r2, BaseOfBSS
ldr r3, BaseOfZero
0
cmp r2, r3
ldrcc r1, [r0], #4
strcc r1, [r2], #4
bcc %B0
mov r0, #0
ldr r3, EndOfBSS
1
cmp r2, r3
strcc r0, [r2], #4
bcc %B1
gocomp
ldr pc, =%F2 ;goto compiler address
2
;===============================
;熄灭led灯GPB5、6
;===============================
; ldr r0, =GPBCON
; ldr r1, =0x00000000
; str r1, [r0]
;===============================
;进行主函数
;===============================
bl Main
b .
InitStacks
;Do not use DRAM,such as stmfd,ldmfd......
;SVCstack is initialized before
;Under toolkit ver 2.5, 'msr cpsr,r1' can be used instead of 'msr cpsr_cxsf,r1'
mrs r0,cpsr
bic r0,r0,#MODEMASK
orr r1,r0,#UNDEFMODE|NOINT
msr cpsr_cxsf,r1 ;UndefMode
ldr sp,=UndefStack ; UndefStack=0x33FF_5C00
orr r1,r0,#ABORTMODE|NOINT
msr cpsr_cxsf,r1 ;AbortMode
ldr sp,=AbortStack ; AbortStack=0x33FF_6000
orr r1,r0,#IRQMODE|NOINT
msr cpsr_cxsf,r1 ;IRQMode
ldr sp,=IRQStack ; IRQStack=0x33FF_7000
orr r1,r0,#FIQMODE|NOINT
msr cpsr_cxsf,r1 ;FIQMode
ldr sp,=FIQStack ; FIQStack=0x33FF_8000
bic r0,r0,#MODEMASK|NOINT
orr r1,r0,#SVCMODE
msr cpsr_cxsf,r1 ;SVCMode
ldr sp,=SVCStack ; SVCStack=0x33FF_5800
;USER mode has not be initialized.
;The LR register will not be valid if the current mode is not SVC mode.
mov pc,lr
;==================================================================
; Memory configuration should be optimized for best performance
; The following parameter is not optimized.
; Memory access cycle parameter strategy
; 1) The memory settings is safe parameters even at HCLK=75Mhz.
; 2) SDRAM refresh period is for HCLK<=75Mhz.
;http://blog.csdn.net/mr_raptor/article/details/6555786
;==================================================================
;BWSCON
DW8 EQU (0x0)
DW16 EQU (0x1)
DW32 EQU (0x2)
WAIT EQU (0x1<<2)
UBLB EQU (0x1<<3)
B1_BWSCON EQU (DW16) ; AMD flash(AM29LV800B), 16-bit, for nCS1
B2_BWSCON EQU (DW16) ; PCMCIA(PD6710), 16-bit
B3_BWSCON EQU (DW16) ; Ethernet(CS8900), 16-bit
B4_BWSCON EQU (DW32) ; Intel Strata(28F128), 32-bit, for nCS4
B5_BWSCON EQU (DW16) ; A400/A410 Ext, 16-bit
B6_BWSCON EQU (DW32) ; SDRAM(K4S561632C) 32MBx2, 32-bit
B7_BWSCON EQU (DW32) ; N.C.
;BANK0CON
B0_Tacs EQU 0x3 ;0clk
B0_Tcos EQU 0x3 ;0clk
B0_Tacc EQU 0x7 ;14clk
B0_Tcoh EQU 0x3 ;0clk
B0_Tah EQU 0x3 ;0clk
B0_Tacp EQU 0x1
B0_PMC EQU 0x0 ;normal
;BANK1CON
B1_Tacs EQU 1;0x0 ;0clk
B1_Tcos EQU 1;0x0 ;0clk
B1_Tacc EQU 6;0x7 ;14clk
B1_Tcoh EQU 1;0x0 ;0clk
B1_Tah EQU 1;0x0 ;0clk
B1_Tacp EQU 0x0
B1_PMC EQU 0x0 ;normal
;Bank 2 parameter
B2_Tacs EQU 1;0x0 ;0clk
B2_Tcos EQU 1;0x0 ;0clk
B2_Tacc EQU 6;0x7 ;14clk
B2_Tcoh EQU 1;0x0 ;0clk
B2_Tah EQU 1;0x0 ;0clk
B2_Tacp EQU 0x0
B2_PMC EQU 0x0 ;normal
;Bank 3 parameter
B3_Tacs EQU 0x1;0 ;0clk
B3_Tcos EQU 0x1;0 ;0clk
B3_Tacc EQU 0x6;7 ;14clk
B3_Tcoh EQU 0x1;0 ;0clk
B3_Tah EQU 0x1;0 ;0clk
B3_Tacp EQU 0x0
B3_PMC EQU 0x0 ;normal
;Bank 4 parameter
B4_Tacs EQU 0x1;0 ;0clk
B4_Tcos EQU 0x1;0 ;0clk
B4_Tacc EQU 0x6;7 ;14clk
B4_Tcoh EQU 0x1;0 ;0clk
B4_Tah EQU 0x1;0 ;0clk
B4_Tacp EQU 0x0
B4_PMC EQU 0x0 ;normal
;Bank 5 parameter
B5_Tacs EQU 0x1;0 ;0clk
B5_Tcos EQU 0x1;0 ;0clk
B5_Tacc EQU 0x6;7 ;14clk
B5_Tcoh EQU 0x1;0 ;0clk
B5_Tah EQU 0x1;0 ;0clk
B5_Tacp EQU 0x0
B5_PMC EQU 0x0 ;normal
; When 100MHz HCLK is used.
;Bank 6 parameter
B6_MT EQU 0x3 ;SDRAM
B6_Trcd EQU 0x1 ;3clk
B6_SCAN EQU 0x1 ;9bit
;Bank 7 parameter
B7_MT EQU 0x3 ;SDRAM
B7_Trcd EQU 0x1 ;3clk
B7_SCAN EQU 0x1 ;9bit
;REFRESH parameter
REFEN EQU 0x1 ;Refresh enable
TREFMD EQU 0x0 ;CBR(CAS before RAS)/Auto refresh
Trp EQU 0x1 ;3clk
Tsrc EQU 0x1 ;5clk Trc= Trp(3)+Tsrc(5) = 8clock
Tchr EQU 0x2 ;3clk
REFCNT EQU 1268;1463;1268 ;HCLK=100Mhz, (2048+1-7.81*100);75M->1463
SMRDATA DATA
DCD (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28)) ;0x2212_1110
DCD ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) ;GCS0 ;0x7ff4
DCD ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) ;GCS1 ;
DCD ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) ;GCS2 ;
DCD ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<
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